In recent years, memory device manufacturers have been fabricating memory devices in which two or more memory device dice are stacked one on top of the other, thereby increasing the uniformity while decreasing the lengths of the leads of the respective memory devices. For example, in a conventional fabrication process, such memory devices can each include a first memory device die and a second memory device die, the first memory device die being configured to be stacked on top of the second memory device die. Each of the first and second memory device dice may be implemented as a dynamic random access memory (DRAM), including one or more memory banks and associated transceivers and control/address logic. The memory devices may each further include a control/address bus having a specified number of control/address bits, a data bus having a specified number of data bits, and a plurality of channels corresponding to the control/address and data buses within each of the first and second memory device dice. In such memory devices, each of the first and second memory device dice can correspond to a separate memory rank, and the stacked first and second memory device dice can represent a two-rank memory stack having the same number of channels as one of the first and second memory device dice.
The memory devices described above can each be implemented within a system memory that includes a memory controller having a memory interface with control/address and data bus connections for interfacing with the control/address and data buses, respectively, of the memory device. Further, the data bus may be partitioned to interface with the number of channels within the respective first and second memory device dice, and the control/address bus may likewise be partitioned to interface with the control/address logic within the respective first and second memory device dice.